This invention relates to a power saving technology for a computer system including a many-core processor chip.
Parallel computer systems including several hundred thousand to several millions of processor cores coupled to one another have been developed in order to perform large-scale scientific and technological simulations. In the parallel computer systems in recent years, a many-core processor chip in which several thousands of processor cores of the same type that are simplified in structure are implemented by virtue of an increase in the degree of integration is used. A representative configuration thereof is constructed by a group of computing nodes including a sub-system of a many-core processor chip and a high-speed network adaptor. The many-core processor chip is coupled to a general-purpose CPU chip and a main storage apparatus via the PCI Express as an input/output device and includes an independent memory, and a high-speed network adaptor.
In a large-scale system coupling some tens of thousands of computing nodes to one another, an overall power consumption is more than 10 megawatts, and a mechanism for suppressing the power is thus necessary. Moreover, when all the cores operate under high loads in a single processor chip, the power and the temperature exceed design upper limits, and a calculation speed thus needs to be adjusted.
Thus, there is known power control using a power saving function for carrying out power consumption management on a core-by-core basis (for example, refer to JP 2012-038347 A and JP 2010-211544 A).
In JP 2012-038347 A, there is a description: “Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in a many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.” As a result, power control can be carried out in accordance with a calculation amount assigned to each core.
Moreover, in JP 2010-211544 A, there is a description: “there is provided a multi-core processor including: a plurality of processor cores; a register configured to store an identification number of a first task group for tasks, a task processing period, and an upper limit period for carrying out a task included in the first task group; a setting circuit configured to extract a second task group including a plurality of tasks processed in parallel out of the tasks included in the first task group, and to set a first processing period for processing the second task group as a second processing period in accordance with power consumption of the processor core for processing the second task group; and a drive circuit configured to change, in accordance with a ratio between the task processing period and the second processing period, a frequency of an operation clock or a power supply voltage supplied to the processor core for processing each task.”